When we talk about the logic circuits, there is a special class of logic which is called sequential logic. Here, the output of the circuit depends not only from the state of the input, but and from the state of the output itself. This kind of sequential logic element is known as Flip-flop. There are many types of flip-flop circuits. Characteristic of these circuits is that they have ability to store (memory) certain logic state. Flip-flops are imlemented with appropriate connection of the basic logic gates.
The SR flip-flop is one of the best known and simplest circuit for storing a bit-information. On Picture 1 are shown the symbol, the schematic symbol and the table of truth of SR flip-flop. The inputs of the circuit are marked with S (set) and R (reset). The outputs are Q and its negation. When we send a pulse on the input S, then we say that the circuit is set. When we send a pulse on the input R, then we say that the circuit is reset. Q' is inverse state of the state of Q (when Q is true, Q' is false). If the inputs S and R are both 0, then the outputs remains the same as the last set or reset to the circuit. As we can see from the table of truth, if S = 1 and R = 0, then output Q = 1. In other case, if S = 0 and R = 1, then output Q = 0. However, if both of the inputs S and R are 1, then the output of the circuit is unpredictible and because of that the state when S = 1 and R = 1 is not allowed.
Picture 1: SR Flip-flop - symbol, schematic symbol and table of truth
The input of this circuit is marked as D (data). The symbol of the D Flip-flop an its table of truth are shown on Picture 2. The other input of the circuit, which signed as >, is actually the clock signal (clk). The logic state of the input D is send to the output only if there is a positive pulse on the clock input. If there is a change of the state of the input D, this change will be not send to the output Q until the next positive pulse of the clock signal.
Picture 2: D Flip-flop - symbol and table of truth
The symbol of the T Flip-flop an its table of truth are shown on Picture 3. The output of this circuit is changing its state for every positive pulse from the clock signal that is send to the input T. This means that the output signal of this circuit have two times lower frequency from the frequency of the input (clock) signal. So, this circuit can be used for dividing the frequency of the input clock signal with ratio 2:1. If we connect two of this circuits in series, then we will have the dividing with ratio 4:1, etc.
Picture 3: T Flip-flop - symbol and table of truth
This circuit have two inputs marked as J and K. The third input (>) is for the clock signal. On Picture 4 are shown the symbol of the JK Flip-flop an its table of truth. If input J = 1 and input K = 0, then when the clock signal have the positive pulse the output Q is set (Q = 1). If J = 0 and K = 1, then in case of the positive pulse of the clock signal the output Q is reset (Q = 0). In the case when both of the inputs J and K are 1, then in case of the positive pulse of the clock signal the output Q is changing its state. And finally, when both of the inputs J and K are 0, then in case of the positive pulse of the clock signal the output Q doesn't change its state. The advantage of this circuit is that there is no unpredictible state as in the case of the RS flip-flop.
Picture 4: JK Flip-flop - symbol and table of truth